The present invention relates to a method for manufacturing a semiconductor device in which trench isolation is provided in an SOI (Silicon On Insulator or Semiconductor On Insulator) substrate for element isolation.
A semiconductor device that has an SOI substrate formed from an insulating film and a semiconductor layer thereon and has an element such as transistor or resistance formed at the SOI substrate is known to be advantageous in that it is capable of implementing an increased operation speed or increased voltage resistance due to reduced parasitic capacitance, and capable of implementing increased reliability due to prevention of latch-up, and the like.
FIG. 14 shows a cross-sectional structure of a conventional semiconductor device, specifically, a semiconductor device having a MOS (Metal Oxide Semiconductor) transistor formed on the SOI substrate.
As shown in FIG. 14, a semiconductor substrate 1 is an SOI substrate in which a substrate base portion 2 and a substrate surface portion 3 are electrically isolated from each other by a first insulating film 4. The substrate base portion 2 and the substrate surface portion 3 are both formed from single crystal semiconductor silicon. The substrate surface portion 3 is covered with a silicon oxide film 5 in the region other than an element formation region. An element isolation groove (hereinafter, referred to as “trench”) 6 is formed through the silicon oxide film 5 and the substrate surface portion 3 at the location corresponding to an element isolation region.
A second insulating film 7 of silicon oxide is formed at the wall surface of the trench 6. The trench 6 having the second insulating film 7 formed at its wall surface is filled with an embedded layer 8 of polycrystalline silicon. The surface of the embedded layer 8 is covered with a third insulating film 9 of silicon oxide. A trench element isolation structure 10 is thus formed from the second insulting film 7, the embedded layer 8 and the third insulating film 9.
A gate electrode 12 is formed on the region of the substrate surface portion 3 surrounded by the trench element isolation structure 10, i.e., on the element formation region, with a gate insulating film 11 interposed therebetween. A pair of impurity diffusion layers 13 serving as source and drain regions are formed on both sides of the gate electrode 12 in the substrate surface portion 3. A MOS transistor 14 is formed from the gate electrode 12, the impurity diffusion layers 13 and the like. Note that, in the conventional semiconductor device, another element such as bipolar element or resistive element may be formed in the element formation region, instead of or in addition to the MOS transistor 14.
FIGS. 15A and 15B are cross-sectional views illustrating the steps of forming the trench element isolation structure in the conventional semiconductor device of FIG. 14.
First, as shown in FIG. 15A, the silicon oxide film 5 and the substrate surface portion 3 are etched using a mask pattern 15, thereby forming the trench 6 extending to the first insulating film 4. For example, this etching is conducted by a reactive ion etching method using a gas such as hydrogen bromide. The mask pattern 15 is formed from a resist film patterned by a normal photolithography technique or from a silicon nitride film or a silicon oxide film.
As shown in FIG. 15B, the substrate surface portion 3 is then thermally oxidized at the wall surface of the trench 6, thereby forming a second insulating film 7 of silicon oxide. Thereafter, the resist film or the silicon nitride film or silicon oxide film used as the mask pattern 15 for etching is removed.
In the aforementioned conventional method for manufacturing a semiconductor device, however, oxygen atoms are introduced into the interface between the first insulating film 4 and the substrate surface portion 3 as well as the interface between the substrate surface portion 3 and the silicon oxide film 5 during thermal oxidation for forming the second insulating film 7. As a result, a silicon oxide film is grown along each interface (see regions RA and RB in FIG. 15B). Oxidation of the single crystal semiconductor silicon of the substrate surface portion 3 causes volume expansion. Therefore, compressive stresses are generated in the portion of the substrate surface portion 3 surrounded by the trench 6, i.e., in the semiconductor layer of the element formation region, thereby producing crystal defects in the semiconductor layer. This problem becomes more remarkable when attempting dimensional reduction of the element, reduction in thickness of the single crystal silicon film serving as the substrate surface portion 3.
In order to solve the aforementioned problem, Japanese Patent Gazette No. 2589209B discloses a method for relieving the stresses causing generation of crystal defects. More specifically, after a trench is formed, a polycrystalline semiconductor film is deposited in the trench in a reduced-pressure vapor phase so as to round a trench corner. A thermal oxide film is formed thereafter. Thus, the stresses are relieved particularly in the lower corner (which corresponds to the region RA of FIG. 15B).
According to the method of the aforementioned Japanese Patent Gazette No. 2589209B, however, the curvature of each corner depends on the coating profile of the polycrystalline semiconductor film. Therefore, the degree of stress relief in the thermal oxidation step after deposition of the polycrystalline semiconductor film varies depending on the coating profile. This means that the aforementioned crystal defects may possibly be generated. Accordingly, the crystal defects are more likely to be generated depending on the degree of process variation, and this may become a critical cause of the reduced yield of the element.